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| EPSRC Reference: |
GR/R65275/01 |
| Title: |
An Integrated Hardware-Software Approach to Single Chip Processor Systems |
| Principal Investigator: |
Professor M O'Boyle |
| Other Investigators: |
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| Researcher Co-investigator: |
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| Project Partner: |
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| Department: |
Sch of Informatics |
| Organisation: |
University of Edinburgh |
| Scheme: |
Standard Research |
| Starts: |
01 January 2002 |
Ends: |
31 December 2004 |
Value (£): |
167,442
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| EPSRC Research Topic Classifications: |
| Parallel Computing |
Systems Methodology and Architecture |
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| EPSRC Industrial Sector Classifications: |
| Electronics |
Information Technologies |
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| Related Grants: |
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| Panel History: |
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Summary |
The research is aiming to address the problem of how to use future silicon technology to produce single chip systems whose performance can extend beyond that which is likely to be achievable from current (super-scalar) architectural approaches. The limit of the necessary low-level instruction parallelism is already being hit and the solution may lie with the support of flexible lightweight multi-threading in the hardware,
However, this is not just a hardware architectural problem. There is reason to believe that multi-threading as evidenced in languages like Java is likely to become a major feature of future applications, but the task of mapping software threads on to hardware ones is not as straightforward as it might appear. In both cases threads exist to expose parallelism, but the characteristics which need to be exploited for software structuring and for hardware efficiency are often dissimilar in function, size and lifetime. it is our belief that dynamic compilation is an exciting new way to approach the mapping problem.
As chip multi-processors provide an opportunity to start with a relatively unconstrained design, there is also considerable scope for an integration of the hardware, the run-time system and the compilation. This is a major theme of the research.
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| Final Report Summary |
The research is aiming to address the problem of how to use future silicon technology to produce single chip systems whose performance can extend beyond that which is likely to be achievable from current (super-scalar) architectural approaches. The limit of the necessary low-level instruction parallelism is already being hit and the solution may lie with the support of flexible lightweight multi-threading in the hardware,
However, this is not just a hardware architectural problem. There is reason to believe that multi-threading as evidenced in languages like Java is likely to become a major feature of future applications, but the task of mapping software threads on to hardware ones is not as straightforward as it might appear. In both cases threads exist to expose parallelism, but the characteristics which need to be exploited for software structuring and for hardware efficiency are often dissimilar in function, size and lifetime. it is our belief that dynamic compilation is an exciting new way to approach the mapping problem.
As chip multi-processors provide an opportunity to start with a relatively unconstrained design, there is also considerable scope for an integration of the hardware, the run-time system and the compilation. This is a major theme of the research.
New Summary
The project has developed feedback directed compiler technology that outperforms all current approaches to program optimisation. It develops a machine learning based approach to Java optimisation that provides significant performance improvements without any on-line overhead and is the first ever piece of work on multi-transformational machine learning based compilation. Finally, this project has developed a novel auto-parallelisation approach to pointer rich programs giving the first truly automatic approach to compiling for embedded chip multi-processor.
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| Further Information: |
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| Organisation Website: |
http://www.ed.ac.uk |
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