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| EPSRC Reference: |
EP/C547861/1 |
| Title: |
Automatic Test Pattern Generation and Scan Insertion for Asynchronous Circuits |
| Principal Investigator: |
Dr A Efthymiou |
| Other Investigators: |
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| Researcher Co-investigator: |
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| Project Partner: |
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| Department: |
Sch of Informatics |
| Organisation: |
University of Edinburgh |
| Scheme: |
First Grant Scheme |
| Starts: |
01 December 2005 |
Ends: |
30 November 2008 |
Value (£): |
94,379
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| EPSRC Research Topic Classifications: |
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| EPSRC Industrial Sector Classifications: |
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| Related Grants: |
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| Panel History: |
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Summary |
The fast evolution in semiconductor technology brings along not only speed and cost benefits, but also hard challenges for circuit and system designers. One of the major challenges is how to distribute the 'clock' signal, a timing reference signal broadcast to the whole chip that dictates when system state is updated and synchronises all information exchanges. An extreme solution is to remove the clock altogether, leading to the asynchronous design style. While there are currently very few fully-asynchronous systems, the semiconductor industry roadmap predicts that, in the near future, conventional integrated circuits will be employing some asynchronous circuits mostly for the communication between blocks that have independent clocks.
Unfortunately, current solutions for post-fabrication testing of asynchronous circuits are not as mature as those for synchronous circuits. This means that it is hard to tell if an asynchronous circuit, or the asynchronous part of a future system, has been fabricated without any faults. As commercial chips must have a "fault-coverage" of nearly 100%, it is clear that the testability of asynchronous circuits must be improved.
The overall aim of this project is to develop a methodology for testing asynchronous circuits and implement a tool that will be able to convert a given circuit into a testable equivalent and produce the sequence of test-vectors required for actually performing the test.
A commonly used method in synchronous design is to add extra circuits (scan-latches) that can aid the testing task. A direct application of the method to asynchronous circuits has already been proposed and it can successfully produce testable circuits, albeit at an extremely high cost, because the number of added scan-latches is enormous. This project will investigate methods for adding the minimum number of scan-latches that will produce a fully testable circuit and explore the trade-offs between cost and test coverage for asynchronous circuits.
By reducing the number of added scan-latches, the task of test-pattern generation becomes harder as the order in which the patterns are applied becomes critical. Thus, the second major objective of the project is to produce a tool that generates test patterns for the asynchronous circuits. Existing tools are designed assuming synchronous operation and thus produce test patterns with a very low fault coverage for asynchronous circuits.
The research has the potential to produce practical tools that will fill in a gap in the existing Electronic Design Automation (EDA) tool range. It is worth noting that the UK is home to a relatively high percentage of the world's asynchronous design community, in both academia and industry, which will directly benefit from this research. Moreover, as testing is considered the Achilles' heel of the asynchronous technology, a successful outcome will help to expand the adoption of this design style to a wider design community
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| Final Report Summary |
The main aim of the research was to develop a methodology for testing asynchronous circuits and implement a tool that will be able to convert a given circuit into a testable equivalent and produce the sequence of test-vectors required for actually performing the test.
The project has contributed a test methodology with some alternative options for the different steps involved. A number of software tools have been developed that help automate the methodology. Specifically two algorithms for selecting the optimal location to insert scan-latches into a circuit have been invented and the corresponding tools were developed. A separate tool which generates the test vectors has also been developed. In addition, a novel method based on initialising sequential asynchronous circuits has been developed, implemented in software and evaluated.
The results show that fault coverage very similar to that of the full-scan method can be achieved with a much lower silicon area overhead. Moreover, in some cases, the test time can also be reduced. The methods and the results have been published in one prestigious journal and four conference publications.
This research will benefit researchers and industry involved in asynchronous systems. A complete flow for testing asynchronous circuits has been implemented. Our tools have not been released yet because they need some minor development work and we don't currently have the capacity to maintain publicly released versions of them. We will evaluate how best they can be exploited by discussing with relevant industrial contacts, such as Silistix Ltd. We eventually plan to make the tools available either using a licensing scheme or posting them as open-source software.
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| Further Information: |
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| Organisation Website: |
http://www.ed.ac.uk |
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