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Details of Grant 

EPSRC Reference: GR/S12036/01
Title: Synthesis and TEsting of Low-Latency Asynchronous circuits (STELLA)
Principal Investigator: Yakovlev, Professor A
Other Investigators:
Kinniment, Professor D Koelmans, Dr AM Russell, Dr G
Researcher Co-Investigators:
Project Partners:
Department: Electrical, Electronic & Computer Eng
Organisation: Newcastle University
Scheme: Standard Research (Pre-FEC)
Starts: 01 April 2003 Ends: 31 March 2006 Value (£): 256,391
EPSRC Research Topic Classifications:
Electronic Devices & Subsys. System on Chip
EPSRC Industrial Sector Classifications:
Related Grants:
Panel History:  
Summary on Grant Application Form
STELLA proposes to develop an overall performance-oriented architecture and design methodology for asynchronous, predominantly control, blocks which will focus on the aspect of minimisation of input-to-output delay. The project will provide a high-productivity design flow, based on circuit compilation, with circuit structures, libraries, algorithms and tools for synthesis and testing of self-timed circuits with low-latency. Methods for incorporating scan circuitry and on-line testing with low speed penalty will be of particular interest. The key contributions of the project are expected to be: a two-tier controller structure, in which the context evaluation control logic is decoupled from input-output triggering logic, and a snooper device for tracking the switching behaviour on parallel busses, enabling on-line testing. Software developed in the course of the project will be interfaced to the industrial CAD toolkits (Cadence), acting as a performance and test oriented asynchronous front end.The project will investigate a series of case studies and produce a demonstrator VLSI circuit, e.g. a controller for an on-chip communication channel, to prove the feasibility of the design technology supporting both productivity and performance. An additional important outcome of the project will be its contribution to the resolution of key tradeoffs in designing systems-on-chips as on-chip networks, particularly: predictability and determinism versus average performance, aggressiveness in speed versus testability and robustness.
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Further Information:  
Organisation Website: http://www.ncl.ac.uk