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Details of Grant 

EPSRC Reference: EP/P013570/1
Title: Parallel Heterogeneous Integration of III-V Devices on Silicon Photonic Chips
Principal Investigator: Sorel, Professor M
Other Investigators:
Researcher Co-Investigators:
Dr Y Ding
Project Partners:
CIP Technologies Compound Semiconductor Tech Global Ltd Fraunhofer UK Research Ltd
Gas Sensing Solutions Ltd Kaiam Corporation (UK) Seagate Technology
University of Southampton
Department: School of Engineering
Organisation: University of Glasgow
Scheme: Standard Research
Starts: 01 March 2017 Ends: 29 February 2020 Value (£): 334,631
EPSRC Research Topic Classifications:
Optoelect. Devices & Circuits
EPSRC Industrial Sector Classifications:
Electronics
Related Grants:
EP/P013597/1
Panel History:
Panel DatePanel NameOutcome
01 Dec 2016 EPSRC ICT Prioritisation Panel Dec 2016 Announced
Summary on Grant Application Form
Photonics is one of the largest and fasted growing markets of the world economy. Optical technologies are key to a vast range of applications from telecommunications networks to sensor and metrology equipment and are being actively developed by industrial giants such as IBM, Intel and Cisco.

In a similar way to the evolution experienced by electronics, the demand for photonics devices with smaller footprint, lower cost and higher functionality has propelled the rapid development of integrated "photonics chips". Thanks to the legacy provided by decades of enormous investments in the electronic industry, silicon is rapidly becoming the standard material platform for photonic integrated chips. However, because of its crystalline structure, silicon is a very poor light emitter and, therefore, truly integrated devices that can emit, process and detect light on-chip still represent a major challenge. III-V semiconductor materials such as InP or GaAs provide far better performance in terms of light emission but cannot compete with silicon in terms of large volume manufacturing and cost. Combining the "best from the two worlds", i.e. heterogeneously integrating III-V light emitters on a silicon material platform, is regarded as a promising solution to circumvent the deficiencies of silicon yet keeping compatibility with industrial silicon manufacturing paradigms to allow scaling to wafer level complex products without requiring a full retooling of the supply chain.

Building on established expertise in photonic integrated devices and transfer printing technologies at Glasgow and Strathclyde universities, this proposal will develop an assembly technique to integrate active III-V membrane devices onto passive silicon photonic integrated circuits. The method will demonstrate parallel transfer of multiple devices with sub-micrometer positional accuracy and scalability to wafer-level production. The developed techniques will exploit fully back-end processes, making them compatible with current foundry standards and therefore commercial interests. Key demonstrators in optical communications, gas sensing and high density data storage will be developed to illustrate the flexibility of the methods and potential across a wide range of application spaces.

The project will benefit from the support from several academic and industrial partners who will provide resources and expertise in key areas such as wafer-scale manufacturing of III-V optical devices (CST), transfer printing system engineering (Fraunhofer), optical transceivers for telecomm and datacentre markets (Huawei), micro-assembly of active/passive photonic systems (Kaiam), integrated photonic devices for HDD data storage (Seagate), mid-IR gas sensors (GSS), large-scale silicon photonics devices (Southampton University).

The proposal aligns with EPSRC's Manufacturing the Future theme and the Photonics for Future Systems priority, and addresses specific portfolio areas such as Manufacturing Technologies, Optical Communications, Optical Devices & Subsystems, Optoelectronic Devices & Circuits, Components & Systems

Key Findings
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