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EPSRC Reference: EP/K008730/1
Title: PAMELA: a Panoramic Approach to the Many-CorE LAndsape - from end-user to end-device: a holistic game-changing approach
Principal Investigator: Furber, Professor S B
Other Investigators:
Lester, Dr DR Kelly, Professor P O'Boyle, Professor M
Topham, Professor N Lujan, Dr M Davison, Professor AJ
Franke, Dr B Ham, Dr DA
Researcher Co-Investigators:
Project Partners:
Agilent Technologies Ltd ARM Ltd Dyson Limited
Foundry Visionmongers Ltd Hewlett Packard Imagination Technologies Ltd UK
Microsoft Oracle Corporation Samsung
Wolfson Microelectronics
Department: Computer Science
Organisation: University of Manchester, The
Scheme: Programme Grants
Starts: 01 March 2013 Ends: 28 February 2018 Value (£): 4,135,048
EPSRC Research Topic Classifications:
Computer Sys. & Architecture VLSI Design
EPSRC Industrial Sector Classifications:
Communications Electronics
Information Technologies
Related Grants:
Panel History:
Panel DatePanel NameOutcome
22 Nov 2012 Programme Grant Interviews - 22 & 23 November 2012 (ICT) Announced
Summary on Grant Application Form
The last decade has seen a significant shift in the way computers are designed. Up to the turn of the millennium advances in performance were achieved by making a single processor, which could execute a single program at a time, go faster, usually by increasing the frequency of its clock signal. But shortly after the turn of the millennium it became clear that this approach was running into a brick wall - the faster clock meant the processor got hotter, and the amount of heat that can be dissipated in a silicon chip before it fails is limited; that limit was approaching rapidly!

Quite suddenly several high-profile projects were cancelled and the industry found a new approach to higher performance. Instead of making one processor go ever faster, the number of processor cores could be increased. Multi-core processors had arrived: first dual core, then quad-core, and so on. As microchip manufacturing capability continues to increase the number of transistors that can be integrated on a single chip, the number of cores continues to rise, and now multi-core is giving way to many-core systems - processors with 10s of cores, running 10s of programs at the same time.

This all seems fine at the hardware level - more transistors means more cores - but this change from one to many programs running at the same time has caused many difficulties for the programmers who develop applications for these new systems. Writing a program that runs on a single core is much better understood than writing a program that is actually 10s of programs running at the same time, interacting with each other in complex and hard-to-predict ways. To make life for the programmer even harder, with many-core systems it is often best not to make all the cores identical; instead, heterogeneous many-core systems offer the promise of much higher efficiency with specialised cores handling specialised parts of the overall program, but this is even harder for the programmer to manage.

The Programme of projects we plan to undertake will bring the most advanced techniques in computer science to bear on this complex problem, focussing particularly on how we can optimise the hardware and software configurations together to address the important application domain of 3D scene understanding. This will enable a future smart phone fitted with a camera to scan a scene and not only to store the picture it sees, but also to understand that the scene includes a house, a tree, and a moving car. In the course of addressing this application we expect to learn a lot about optimising many-core systems that will have wider applicability too, and the prospect of making future electronic products more efficient, more capable, and more useful.
Key Findings
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Organisation Website: http://www.man.ac.uk