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Details of Grant 

EPSRC Reference: EP/I013539/1
Title: Dynamic Adaptation in Heterogeneous Multicore Embedded Processors
Principal Investigator: Topham, Professor N
Other Investigators:
Franke, Dr B O'Boyle, Professor M Haas, Professor H
Researcher Co-Investigators:
Project Partners:
Associated Compiler Experts Virage Logic
Department: Sch of Informatics
Organisation: University of Edinburgh
Scheme: Standard Research
Starts: 01 November 2010 Ends: 31 July 2014 Value (£): 1,217,557
EPSRC Research Topic Classifications:
Artificial Intelligence Digital Signal Processing
System on Chip
EPSRC Industrial Sector Classifications:
Information Technologies
Related Grants:
Panel History:
Panel DatePanel NameOutcome
07 Sep 2010 ICT Prioritisation Panel (Sept 2010) Announced
Summary on Grant Application Form
The overall objective of this project is to investigate new and novel methods of automating the design, of both the hardware and software, of embedded systems to enable the timely creation of future generations of high-performance low-power digital appliances. This is a vertically-integrated project, which brings together research in compilers, architectures, signal processing, and an economically-important emerging application area.Embedded processors are an integral part of our everyday lives; from smart phones and flash memory sticks, to wireless communications, automotive computing, bio-medical devices, and many more. Future embedded processors will require significantly higher performance than the processors we have today. However, this must be achieved whilst also increasing their energy efficiency, as such systems are increasingly used in mobile or battery-operated devices.Performance cannot be increased simply by clocking devices at a higher frequency, as this significantly reduces energy efficiency.Previous research has shown that customizing a processor according to its application can provide a significant performance boost whilst simultaneously reducing energy consumption. Similarly, the use of multi-core processors, which can be specialized in heterogeneous ways, offers additional performance in a more energy-efficient way than can be achieved simply by the homogeneous replication of a fixed processor.The first challenge with application-specific processors, which is compounded in heterogeneous multi-core systems, is the vast array of possible designs from which to choose. This increasing complexity of the design space of computer systems, coupled with the drive for lower energy consumption, means that manual approaches to design are no longer feasible. Instead, by automating the process of searching the design space, it becomes possible to find the best designs. However, this approach is computationally intractable, due to the sheer number of designs that must be considered. There is now strong evidence, from our prior work and from others, that machine learning can provide a fast track to design-space exploration in both processor design and compiler design.The second challenge addressed by this project is variability in behaviour. For example, a broadband modem may wish to adapt its behaviour to the environmental conditions affecting signal quality. At the silicon level, factors such as temperature, process variation and operating voltage will affect the performance and energy consumption of the device. Devices that are able to adapt their hardware and software behaviour to meet these changing circumstances will not be constrained by worst-case analysis at design time, but will be able to tune their behaviour dynamically to meet actual real-time constraints. It is widely accepted that variability is a growing concern that requires a new approach. This project examines how dynamic adaptation in software and hardware can solve this problem. This will involve a combination of just-in-time compilation, to create more dynamic software, as well as just-in-time instruction set re-synthesis, to create dynamic processors.A key aspect of this project is the synergy between new design methods and an emerging application; in this case LED-based Visible Light Communication (VLC). The use of LED lighting is growing rapidly, due its low energy consumption. LED light can also be modulated to carry a digital payload at speeds even higher than 100 Mbps. However, this presents a major computational challenge, which we aim to address using the dynamically adaptable customized multi-core processors and compilers outlined above. We aim to extend the use of machine learning from off-line (i.e. performed at design time) to on-line (i.e. performed during system operation). Designs will be fabricated in silicon to demonstrate the impact of our research, and to enable real-time experimentation.
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